1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device and corresponding driving method for displaying an image on only a part of a panel.
2. Discussion of Related Art
Various flat panel display devices such as a Liquid Crystal Display device (LCD), a Plasma Display Panel (PDP), and an Electro Luminescent Display Device (ELD) are currently being used in as display devices in different types of device. The LCD device is most widely used as a portable image display device due to its excellent image quality, its light weight, its slimness, and its low power consumption. Further, the LCD device is being used as a television monitor, a notebook computer, etc.
Recently, so as to reduce the cost of manufacturing the LCD device, a gate-on-glass (GOG) type LCD has been proposed. The GOG type LCD includes a liquid crystal panel on which a gate driver is mounted. Further, in the GOG type LCD, the gate driver is manufactured simultaneously with the liquid crystal panel. In addition, the GOG type LCD may include a liquid crystal panel on which a data driver is mounted. The GOG type LCD will be now described with reference to FIG. 1.
As shown in FIG. 1, a related art GOG type LCD includes a liquid crystal panel 2 on which an image is displayed. The liquid crystal panel 2 includes a display region 22 and a gate driver 4. The gate driver 4 is disposed at an edge (left edge) of one side of the display region 22 and is adjacent to the display region 22.
In addition, the display region 22 of the liquid crystal panel 2 includes thin film transistors TFT, which are respectively formed at pixel regions divided by a plurality gate and data lines (not shown). Also, each thin film transistor is electrically connected to a corresponding data line and gate line. Further, the gate driver 4 is electrically connected to respective gate lines on the display region 22.
The GOG type LCD of FIG. 1 also includes a printed circuit board 12 connected to the liquid crystal panel 2 through tape carrier packages (TCPs) 7A-7C. In addition, corresponding data driver integrated circuit (IC) chips 6A-6C are mounted on the TCPs 7A-7C. The data driver IC chips 6A-6C division-drive a plurality of data lines on the liquid crystal panel 2.
To do this, the data driver IC chips 6A-6C are electrically connected to parts of a plurality of data lines on the liquid crystal panel 2 by corresponding TCPs 7A-7C, respectively. As shown, a timing controller 8 is mounted on the printed circuit board 12 and controls the gate driver 4 and the data driver IC chips 6A-6C. To do this, the timing controller 8 is electrically to the data driver IC chips 6A-6C and the gate driver 4 via one of the TCPs 7A-7C.
Next, as shown in FIG. 2, the gate driver 4 includes a plurality of shift register stages S/R1-S/Rn, which are dependently coupled to each other. The same number of gate lines is present at the liquid crystal panel 2 corresponding to the number of shift register stages S/R1-S/Rn. Further, an output signal generated from each of the shift register stages S/R1-S/Rn is supplied to an input terminal of a next shift register stage to drive it. Also, an output signal generated from each of the shift register stages S/R1-S/Rn is supplied to a corresponding gate line.
As shown in FIG. 3, the output signals of the shift register stages S/R1-S/Rn exclusively include enable signals, which are sequentially delayed. Further, a gate start pulse GSP is input to an input terminal of the first shift register state S/R1 among the shift register stages S/R1-S/Rn, which are dependently connected to each other. In addition, a shifting operation of the shift register stages S/R1-S/Rn is performed according to the gate start pulse GSP. The gate start pulse GSP is synchronous with a vertical synchronous signal and has a width corresponding to a time period of a horizontal synchronous signal.
Moreover, one of two clocks C1 and C2 is input to the shift register stages S/R1-S/Rn. In addition, the first clock C1 is input to odd-numbered shift register stages S/R1, S/R3, . . . , S/Rn-1, whereas the second clock C2 is input to even-numbered shift register stages S/R2, S/R4, . . . , S/Rn. Further, the two clocks C1 and C2 have an inverse phase to each other. Also, at least 3 clocks (for example, 3 or 4 clocks) are input to the shift register stages S/R1-S/Rn in common, or a part of 3 clocks can be selective supplied thereto. In this instance, the at least 3 clocks have a phase, which is sequentially delayed.
Further, the shift register stages S/R1-S/Rn latch a gate start pulse GSP supplied to an input terminal or an output signal of a previous shift register stage in response to the input clock C1 or C2. Through a latch operation of the shift register stages S/R1-S/Rn, as shown in FIG. 3, sequentially shifted gate signals GL1 through GLn are correspondingly supplied to a plurality of gate lines on the liquid crystal panel 2.
Also, the gate signals GL1-GLn from the shift register stages S/R1-S/Rn sequentially enable the plurality of gate lines on the liquid crystal panel 2 to sequentially turn on the thin film transistors line by line. Accordingly, data voltages on the plurality of data lines are sequentially supplied to pixels on the liquid crystal panel 2 line by line to display an image.
In addition, in the LCD device, the image is often displayed at a part of the display region 22 of the liquid crystal panel 2. For example, the image can be display at a center of the display region 22. In this instance, the GOG type LCD performs a complex control operation for the gate driver 4, the data driver IC chips 6A-6C, and the timing controller 8 to write a data voltage of a black level in the non-image section of the display region 22. Thus, the GOG type LCD unnecessarily increases the power consumption.